The present invention relates to a data transfer circuit for a semiconductor integrated circuit and, more particularly, to a data transfer circuit for a computer having a data transfer data bus line.
Conventionally, a microcomputer integrated on a semiconductor substrate reads out and executes a program from a ROM (Read Only Memory). FIG. 7 shows the arrangement of a conventional microcomputer around the ROM. In FIG. 7, binary data of a ROM 2 addressed by a program counter 1 are output parallel onto a data bus 3 and sent to an instruction decoder 4.
In the microcomputer having this arrangement, data flowing through the data bus is generally fixed to a positive or negative logic level. If data on the data bus line 3 is illicitly read out by bringing a probe or the like into contact with the data bus, a program stored in the ROM 2 can be undesirably estimated to pose a security problem.